Reference is made to U.S. Pat. No. 7,491,579, filed on even date herewith by Gary S. Delp and George Wayne Nation for “Composable System-in-Package Integrated Circuits and Process of Composing the Same” and assigned to the same assignee as the present invention, the content of which is hereby incorporated by reference in its entirety. The Delp et al. application describes use of configurable base platforms in a system-in-package (SIP).
Conventional ICs had been fabricated by foundries according to designs from device manufacturers. The design process required extensive design and development procedures for placement of elements, signal routing and timing to achieve correct operation of the IC.
More recently, configurable base platforms have become widely used as efficient and economic alternatives to traditional ICs. Configurable base platforms are characterized by a transistor fabric and at least some standard modules that are configurable by the addition of metallization layers or firmware into a functional device. Usually, the configurable base platform included a transistor fabric which is configured to implement a device manufacturer's (customer's) unique circuits, called “customer intellectual property” or simply “customer IP.” In the aforementioned Delp et al. application, we describe use of a configurable base platform that does not have many of the standard modules, such as large memory, input/output (I/O) modules, processors, etc. Instead, standard die provide these standard functions, and the die and platform are packaged together as a SIP.
The present invention is directed to a base platform that includes both ASIC and FPGA features, and to a process of configuring the platform to a usable device. The hybrid platform thus provides the advantage of the speed of ASICs and the ease of expansion and modification of FPGAs. While combined ASIC and FPGA packages are known, there is a need for a configurable base platform with ASIC and FPGA features and a process that allows customer to configure both the ASIC and FPGA features of such base platforms.